On-board Decoder for S-AIS VHF Receiver

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  • Advantages
    • Algorithm available on low-power FPGA platforms
    • Reduces latency in data detection and fusion
    • Eliminates downlink Doppler compensation
    • Reduced downlink power/ bandwidth
    • Significant increase in messages decoded
    • Supports base-band waveform capture

  • Methodology
    • Parallel non-coherent demodulators structure
    • CRC validation of high SINR messages (Group-I)
    • Syndrome decoding of stronger of low SINR messages (Group-II)
    • Interference cancellation (IC) parameters enabled coherent detection (ICPECD) of Group-II messages*
    • IC of Group-I messages to recover messages from IC-residual*
    • Field-of-view and vessel track-based validation of Group-II messages

  • Based on AMD Zynq XC7Z030 SoC and Analog Devices AD9364 RF transceiver
  • Supports AIS Channels 87B and 88B
  • LVDS interface with On-Board Computer (OBC) for waveform and decoded message upload
  • RS422 interface with OBC for telemetry
  • <8W power consumption
  • Decoded AIVDM messages interpreted by an Open Source Chartplotter:
    * Enhanced detection IP available on AMD Zynq UltraScale+ XCZU9EG-2 MPSoC