Key Advantages
- Algorithm available on low-power FPGA platforms
- Reduces latency in data detection and fusion
- Eliminates downlink Doppler compensation
- Reduced downlink power / bandwidth
- Significant increase in messages decoded
- Supports base-band waveform capture
Decoding Methodology
- 1 Parallel non-coherent demodulators structure
- 2 CRC validation of high SINR messages (Group-I)
- 3 Syndrome decoding of stronger of low SINR messages (Group-II)
- 4 Interference cancellation (IC) parameters enabled coherent detection (ICPECD) of Group-II messages*
- 5 IC of Group-I messages to recover messages from IC-residual*
- 6 Field-of-view and vessel track-based validation of Group-II messages
* Enhanced detection IP available on AMD Zynq UltraScale+ XCZU9EG-2 MPSoC
System Specifications
| Core Processor & RF | AMD Zynq XC7Z030 SoC & Analog Devices AD9364 RF transceiver |
| Supported Channels | AIS Channels 87B and 88B |
| OBC High-Speed Data | LVDS interface with On-Board Computer (OBC) for waveform and decoded message upload |
| OBC Telemetry | RS422 interface with OBC for telemetry |
| Power Consumption | < 8W |
Open Source Chartplotter Interpretation
Decoded AIVDM messages interpreted in real-time by an Open Source Chartplotter:
S-AIS On-board Decoder Hardware Unit