Digital Beamformer Hardware Assembly
Compact 8-patch antenna array integration powered by quad AD9361 transceivers and Spartan-6 FPGA architecture.
Technical Specifications
Detailed RF front-end parameters, array configuration, receiver performance metrics, and digital processing architecture:
Antenna Array
8-patch antenna elements arranged in 2 rows × 4 columns.
Dimensions & Spacing
Patch element dimensions: 23.71 × 23.71 × 7.35 mm (L × W × H) with 70.5 mm element spacing.
RF Front-End Tuning
S-band operation: Transmit (Tx) at 2.67–2.69 GHz; Receive (Rx) at 2.5–2.52 GHz or 2.56–2.59 GHz.
IF Interface Support
Supports interfaces with 50 kHz (near ZIF) or 70 MHz IF signals.
Channel Bandwidth
Maximum channel bandwidth of 15 kHz at 50 kHz IF, and 200 kHz at 70 MHz IF.
Boresight Gain & Side Lobes
Tx/Rx boresight gain better than 15 dBi. Side lobe specification compliant with ITU-R Rec S 580-5.
Sensitivity & Combining Gain
−136 dBm receive sensitivity with up to 8.5 dB SNR coherent receiver combining gain.
Dynamic Beam Steering
Real-time dynamic steering for mobility platforms using on-board tilt sensor/compass (HMC6343) and GPS receiver (NEO-M8).
Core Hardware Architecture
High-efficiency processing board featuring 4× AD9361 RF transceivers integrated with a Xilinx/AMD Spartan-6 XC6SLX100 FPGA.