On-board Decoder for S-AIS VHF Receiver

  • Advantages
    • Algorithm suited for FPGA platform
    • Reduces latency in data detection and fusion
    • Eliminates downlink Doppler compensation
    • Reduced downlink power/ bandwidth
    • Significant increase in messages decoded
    • Supports base-band waveform capture

  • Methodology
    • Parallel non-coherent demodulators structure
    • CRC validation of high SINR messages (Group-I)
    • Syndrome decoding of stronger of low SINR messages (Group-II)
    • Field-of-view and vessel track-based validation of Group-II messages

  • Based on Xilinx Zynq XC7Z030 SoC and Analog Devices AD9364 RF transceiver
  • Supports AIS Channels 87B and 88B
  • <7W power consumption
  • Decoded AIVDM messages interpreted by an Open Source Chartplotter: